Heterogeneous integration using wafer-to-wafer stacking with die size adjustment
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United States of America Patent
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Jan 30, 2018
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app pub date -
May 6, 2016
filing date -
May 6, 2016
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Abstract
A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer using a bonding material.
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