Junction gate field-effect transistor (JFET) having source/drain and gate isolation regions
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United States of America Patent
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Jan 30, 2018
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app pub date -
Jul 2, 2014
filing date -
May 13, 2013
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Abstract
A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions.
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