Gate cut on a vertical field effect transistor with a defined-width inorganic mask
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United States of America Patent
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Jan 30, 2018
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app pub date -
Jun 30, 2016
filing date -
Jun 30, 2016
priority date (Note) -
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Abstract
A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.
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