Substrate structure for packaging chip
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United States of America Patent
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Jan 30, 2018
Issued Date -
N/A
app pub date -
Jul 13, 2017
filing date -
Apr 15, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A substrate structure including a carrier and a substrate is provided. The carrier includes a release layer, a dielectric layer and a metal layer. The dielectric layer is disposed between the release layer and the metal layer. The substrate includes a packaging region and a peripheral region. The peripheral region is connected to the packaging region and surrounds the packaging region. The peripheral region or the packaging region has a plurality of through holes. The substrate is disposed on the carrier. The release layer is located between the substrate and the dielectric layer. The release layer and the dielectric layer are filled in the through hole such that the substrate is separably attached to the carrier.
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