Integrated circuit with self-verification function, verification method and method for generating a BIST signature adjustment code
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United States of America Patent
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Feb 6, 2018
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app pub date -
Jun 29, 2015
filing date -
Jul 7, 2014
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Abstract
An integrated circuit includes a Built-In Self-Test (BIST) circuit, a predetermined signature pattern and a Read Only Memory (ROM), wherein the predetermined signature pattern is stored in the integrated circuit. The ROM stores at least effective information and a BIST signature adjustment code, the BIST signature adjustment code is irrelevant to any functional information stored in the ROM; wherein the BIST circuit is used to test content stored in the ROM to generate a signature pattern, and compare the signature pattern with the predetermined signature pattern to judge if the content stored in the ROM has error.
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