Method of manufacturing stacked nanowire MOS transistor

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United States of America Patent

PATENT NO 9892912
SERIAL NO

14688788

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Abstract

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Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

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Patent Owner(s)

Patent OwnerAddress
INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES100029 BEIJING CITY CHAOYANG DISTRICT BEITUCHENG WEST ROAD NO 3 CHINESE ACADEMY OF SCIENCES INSTITUTE OF MICROELECTRONICS MUNICIPAL DISTRICT BEIJING CITY 100029

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Dapeng Beijing, CN 58 328
Fu, Zuozhen Beijing, CN 7 174
Ma, Xiaolong Beijing, CN 54 289
Qin, Changliang Beijing, CN 13 124
Yin, Huaxiang Beijing, CN 109 1161

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