Multi-core hardware semaphore in non-architectural address space

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United States of America Patent

PATENT NO 9898303
SERIAL NO

14281585

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Abstract

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A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

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Patent Owner(s)

  • VIA TECHNOLOGIES, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Henry, G Glenn Austin, US 410 6632
Parks, Terry Austin, US 256 4791

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