Semiconductor device having SOI substrate

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United States of America Patent

PATENT NO 9899448
SERIAL NO

15064686

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Abstract

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There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

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Patent Owner(s)

Patent OwnerAddress
LAPIS SEMICONDUCTOR CO LTD2-4-8 SHINYOKOHAMA KOUHOKU-KU YOKOHAMA 222-8575
INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION1-1 OHO TSUKUBA-SHI IBARAKI 305-0801

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Arai, Yasuo Ibaraki, JP 18 181
Kasai, Hiroki Miyagi, JP 15 41
Okihara, Masao Tokyo, JP 32 365

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