Compact CMOS device isolation
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United States of America Patent
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Feb 20, 2018
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N/A
app pub date -
Dec 8, 2016
filing date -
Jun 30, 2014
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Abstract
An integrated circuit uses a compact CMOS device isolation scheme which forms a ring of N-well housing PMOS devices to encircle the P-well housing NMOS devices in a circuit block. An N-type buried layer is formed under the P-well and extends partially under the surrounding N-well. The compact CMOS device isolation scheme eliminates the use of a deep N-well ring around the circuit block. Therefore, the circuit blocks of the integrated circuit can be formed with reduced silicon area and the die size for implementing the integrated circuit is reduced.
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