Fan-out packages including vertically stacked chips and methods of fabricating the same
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United States of America Patent
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Feb 27, 2018
Issued Date -
N/A
app pub date -
Feb 9, 2017
filing date -
Aug 22, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A fan-out package may include a core supporter having a through hole, a first semiconductor chip disposed on a first surface of the core supporter in a way that a portion of the first semiconductor chip is exposed by the through hole, a second semiconductor chip disposed on a second surface of the core supporter, a first photosensitive dielectric layer disposed on the first surface of the core supporter to cover the first semiconductor chip, a second photosensitive dielectric layer disposed on the second surface of the core supporter to cover the second semiconductor chip and to fill the through hole, a first trace pattern disposed on the second photosensitive dielectric layer, and a first conductive via penetrating the second photosensitive dielectric layer in the through hole to be connected to both of the first trace pattern and the first semiconductor chip.
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