Method for optimizing management of standby of a microprocessor enabling the implementation of several logical cores and computer program implementing such a method
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United States of America Patent
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Mar 6, 2018
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N/A
app pub date -
May 13, 2011
filing date -
May 19, 2010
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Abstract
The subject of the invention is in particular the optimization of standby management of a part of a microprocessor allowing implementation of at least two logic cores, said at least one microprocessor comprising means for placing at least one resource non common to said at least two logic cores on standby. After having determined (400) a desired standby state for each of said at least two logic cores, said desired standby state of one of said at least two logic cores is compared with the said desired standby state of the other of said at least two logic cores. In response to said comparison, instructions preparing for said placement on standby and/or allowing the restoration of said one of said at least two logic cores are launched (420).
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