Memory buffer with one or more auxiliary interfaces
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United States of America Patent
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Mar 6, 2018
Grant Date -
Aug 18, 2016
app pub date -
Apr 25, 2016
filing date -
Apr 11, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center.
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