NAND flash memory and fabrication methods thereof
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United States of America Patent
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Mar 6, 2018
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app pub date -
Aug 23, 2016
filing date -
Dec 10, 2015
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Abstract
A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.
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