Method of fabricating a charge-trapping gate stack using a CMOS process flow
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United States of America Patent
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Mar 6, 2018
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app pub date -
Oct 26, 2016
filing date -
Feb 6, 2014
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Abstract
A method of fabricating a memory device is described. Generally, the method includes forming a channel from a semiconducting material overlying a surface of a substrate, and forming dielectric stack on the channel. A first cap layer is formed over the dielectric stack, and a second cap layer including a nitride formed over the first cap layer. The first and second cap layers and the dielectric stack are then patterned to form a gate stack of a device. The second cap layer is removed and an oxidation process performed to form a blocking oxide over the dielectric stack, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
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