Method and apparatus for performing a bus lock and translation lookaside buffer invalidation
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United States of America Patent
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Mar 13, 2018
Issued Date -
N/A
app pub date -
Oct 23, 2014
filing date -
Oct 25, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.
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