Semiconductor device with electrical overstress (EOS) protection

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United States of America Patent

PATENT NO 9917080
SERIAL NO

13871526

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Abstract

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A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.

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Patent Owner(s)

Patent OwnerAddress
QORVO US INC7628 THORNDIKE ROAD GREENSBORO NC 27409

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ritenour, Andrew P Colfax, US 32 2238

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