Circuit for generating stepped-down voltage
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United States of America Patent
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Mar 20, 2018
Issued Date -
N/A
app pub date -
Mar 7, 2016
filing date -
Sep 26, 2013
priority date (Note) -
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Abstract
A circuit includes a PMOS transistor having a source coupled to an input node and a drain coupled to an output node, a control circuit operating with a voltage of an internal line to control a gate voltage of the PMOS transistor, a comparator operating with the voltage of the internal line to cause a comparator output to change from a first state to a second state in response to a drop of voltage of the input node, a switch circuit configured to connect the input node to the internal line when the comparator output is in the first state, and to connect the output node to the internal line when the comparator output is in the second state, and a block circuit configured to block a path from the output node to the input node through the PMOS transistor when the comparator output is in the second state.
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