Generation of random address mapping in non-volatile memories using local and global interleaving
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United States of America Patent
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Mar 20, 2018
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app pub date -
Dec 11, 2015
filing date -
Jul 14, 2015
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Abstract
Systems and methods for generating random address mapping in non-volatile memories using local and global interleaving are provided. One such method for generating a random address mapping for a non-volatile memory (NVM) involves identifying a number of bits (N) in a physical address space of the NVM, selecting G bit(s) of the N bits to be used for global interleaving, where G is less than N, determining a number of bits (N−G) to be used for local interleaving, mapping the G bit(s) using a mapping function for global interleaving, interleaving (N−G) bits using an interleaving function for local interleaving, and generating a combined mapping comprising the mapped G bit(s) and the interleaved (N−G) bits.
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