Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout
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United States of America Patent
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Mar 20, 2018
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Dec 21, 2015
filing date -
Jan 20, 2014
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Abstract
A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values.
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