Security data path verification

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United States of America Patent

PATENT NO 9922209
SERIAL NO

15269919

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Abstract

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A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INCSAN JOSE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Björk, Magnus Göteborg, SE 3 10
Campos, Caio Araújo Teixeira Austin, US 3 10
Coelho, Claudionor Jose Nunes Menlo Park, US 3 10
Loh, Lawrence Milpitas, US 17 187
Purri, Victor Markus Austin, US 5 13

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