Semiconductor memory device having a plurality of mosfets controlled to be in an active state or a standby state
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United States of America Patent
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Mar 20, 2018
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N/A
app pub date -
Sep 12, 2014
filing date -
Dec 24, 2002
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Abstract
A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells and a plurality of MOSFETS. The MOSFETs are controlled by a control signal to be in one of an active state or a standby state. Part of the MOSFETs are arranged along one end of the memory array and the other parts of the MOSFETs are arranged along another end of the memory array. The other end of the memory array is opposite to the one end of the memory array. The MOSFETs are controlled by the control signal to be turned ON in the active state and to be turned OFF in the standby mode.
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