Multiport memory, memory macro and semiconductor device
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United States of America Patent
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Mar 20, 2018
Issued Date -
N/A
app pub date -
Apr 6, 2017
filing date -
Jun 8, 2016
priority date (Note) -
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Abstract
A multiport memory includes an address control circuit, a memory array, a data input-output circuit and a control circuit and first and second address signals and a clock signal are input through two ports. The address control circuit includes first and second latch circuits, a selection circuit, a decode circuit and a word line drive circuit. The first address signal input through one port is input into the first latch circuit and the second address signal input through the other port is input into the selection circuit. The selection circuit selects one of the first and second address signals, the second latch circuit latches and outputs the selected address signal to the decode circuit. The word line drive circuit drives a word line on the basis of an output signal from the decode circuit.
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