Resistance variable memory apparatus and read circuit and method therefor
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United States of America Patent
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Mar 20, 2018
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N/A
app pub date -
May 30, 2017
filing date -
Nov 18, 2016
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Abstract
A resistance variable memory apparatus in accordance with an embodiment may include a memory cell array and a read circuit. The memory cell array may include a plurality of resistance variable memory cells coupled between a plurality of word lines and a plurality of bit lines. The read circuit may couple a word line, to which a selected resistance variable memory cell is coupled, to a first ground voltage supply terminal for a preset first time period before an amount of current flowing through the selected resistance variable memory cell is detected. The read circuit may couple a bit line, to which the selected resistance variable memory cell is coupled, to a power voltage supply terminal for a preset second time period, in a read operation.
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