Volatile latch circuit with tamper resistant non-volatile latch backup
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United States of America Patent
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Mar 20, 2018
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N/A
app pub date -
Jan 17, 2017
filing date -
Jan 17, 2017
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Abstract
A one-time programmable (OTP) latch includes a memory cell having a first non-volatile (NV) resistive element and a second NV resistive element, cross-coupled inverter circuitry, a first transistor having a first current electrode coupled to a first node of the cross-coupled inverter circuitry and a second current electrode coupled to a first terminal of the first NV resistive element, and a second transistor having a first current electrode coupled to a second node of the cross-coupled inverter circuitry, different from the first node, and a second current electrode coupled to a first terminal of the second NV resistive element. The OTP latch also includes write circuitry coupled to the memory cell and configured to program only one of the first NV resistive element or the second NV resistive element to an OTP state while the cross-coupled inverter circuitry is isolated from the memory cell by the first and second transistors.
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