Integrated circuit wafer integration with catalytic laminate or adhesive
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United States of America Patent
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Mar 20, 2018
Issued Date -
N/A
app pub date -
Nov 12, 2016
filing date -
Nov 12, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.
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