Semiconductor device including power MOS transistor
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United States of America Patent
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Mar 20, 2018
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N/A
app pub date -
Mar 10, 2017
filing date -
Mar 14, 2016
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Abstract
An n-channel power MOS transistor having a gate electrode is formed in an element formation region defined in a semiconductor substrate. A p-type guard ring region is formed in a terminal region. A plurality of p-type column regions are formed from the bottom of the p-type base region to a further deeper position. The column region located in the outermost periphery and the p−-type guard ring region are spaced apart from each other by a distance. A gate electrode lead-out portion electrically coupled to the gate electrode is formed in the p−-type guard ring region.
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