Importance

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Abstract

Main memory access from a CPU is reduced, and thus an increase in speed of data processing is achieved. Provided is a reconfigurable device (20) connected to a main memory (600). The reconfigurable device (20) includes a plurality of logic sections connected to each other by an address line or a data line. Each of the logic sections includes a plurality of address lines, a plurality of data lines, an address decoder that decodes addresses input from part of the plurality of address lines, and a memory cell array unit that includes a plurality of memory cells specified by decode lines of the address decoder, and outputs data read from the specified memory cells to the data lines. An address line of the memory cell array unit is connected to a data output line (RD1) of the main memory.

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First Claim