Dynamic flip-flop and multiplexer for sub-rate clock data serializer

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United States of America Patent

PATENT NO 9924466
SERIAL NO

14709395

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Abstract

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Methods and systems provide a multiplexing cell and a multiplexing cell system for data serialization. The multiplexing cell may be dynamic D-type flip flop having a single phase clock signal (CLK) and a select input (SEL). An input to the multiplexing cell may be passed to an output if CLK is high and SEL are both high. Otherwise, the output of each multiplexing cell may be in a high impedance state. A multiplexing cell system may include one or more of the multiplexing cells and be configured to provide serialization of input data at high data rates with reduced power consumption. Sub-rate clocks, which may be used by at least a portion of a serialization chain, may reduce power consumption allow for less complex clock generation and distribution circuitry. The multiplexing cell and/or multiplexing cell system find application in, among other things, equalization to offset effects of channel imperfections.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Leuciuc, Adrian Luigi Frederick, US 4 21

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