High speed voltage level shifter
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 17, 2018
Issued Date -
N/A
app pub date -
Dec 2, 2016
filing date -
Jun 30, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully