Importance

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Abstract

A decision-directed phase detector (DDPD) to compare an input signal including clock and data components with a reference signal set to a clock crossover value, and generate a first compared output signal designating a transition of the input signal through the clock crossover value. The DDPD may also receive the first compared output signal and generate a phase adjustment signal, and compare the input signal with the reference signal set to a positive offset clock crossover value of the clock crossover value offset by a positive offset value, and generate a positive offset compared output signal designating a transition of the input signal through the positive offset clock crossover value. The DDPD may further generate a valid transition signal to route the phase adjustment signal to a clock generation circuit when the positive offset compared output signal transitions over a clock period.

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First Claim