Low clock power data-gated flip-flop
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United States of America Patent
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May 8, 2018
Issued Date -
N/A
app pub date -
Jun 2, 2016
filing date -
Jun 2, 2016
priority date (Note) -
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Abstract
A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.
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