Lower power high speed decoding based dynamic tracking for memories
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United States of America Patent
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May 22, 2018
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app pub date -
Sep 7, 2016
filing date -
Sep 7, 2016
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Abstract
A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.
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