Semiconductor device and a method of operating the same
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United States of America Patent
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May 29, 2018
Issued Date -
N/A
app pub date -
Jan 25, 2017
filing date -
Jan 25, 2016
priority date (Note) -
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Abstract
A semiconductor device includes a power gating circuit including a synchronous reset flip-flop, a retention circuit including a retention flip-flop, a clock management circuit configured to provide an operation clock to the power gating circuit and the retention circuit, and a power management circuit configured to transmit a power gating control signal to the power gating circuit, the retention circuit, and the clock management circuit. The power gating circuit is activated to signal entry to a power reduction mode. The retention circuit retains states of the semiconductor device. Upon exit from the power reduction mode, the power management circuit is configured to complete a reset operation of the power gating circuit before signaling the retention circuit to cancel a retention state and restore the states of the semiconductor device.
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