Memory system

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United States of America Patent

PATENT NO 9990246
SERIAL NO

13977653

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Abstract

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Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nachimuthu, Murugasamy K Beaverton, US 120 1269
Nale, Bill Livermore, US 74 1024
Quach, Tuan M Fullerton, US 19 171
Zhu, Jun Mountain View, US 689 4956

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