Dual channel memory

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United States of America Patent

PATENT NO 9997640
SERIAL NO

15252250

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Abstract

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Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.

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Patent Owner(s)

  • EMPIRE TECHNOLOGY DEVELOPMENT LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Luo, Zhijiong Poughkeepsie, US 255 4486

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