Output buffer circuit and memory device including the same
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United States of America Patent
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Jun 12, 2018
Issued Date -
N/A
app pub date -
Aug 28, 2017
filing date -
Nov 2, 2016
priority date (Note) -
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Abstract
An output buffer circuit may include a pulse generator, a transmitter, and an emphasis controller. The pulse generator generates a pulse signal for determining an emphasis execution period. The transmitter may receive an input data and to have a first output resistance value, which is determined by the input data and a resistance calibration code, and to have a second output resistance value different from the first output resistance value, which is determined by the input data and an emphasis code different from the resistance calibration code for executing an emphasis operation during the emphasis execution period, based on the pulse signal. The emphasis controller provides the resistance calibration code or the emphasis code to the transmitter based on the pulse signal. The emphasis code may include a first code determined by the input data regardless of the resistance calibration code.
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