Method for incrementally increasing the collector area of a lateral PNP transistor during electrical testing of an integrated device on wafer
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United States of America Patent
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Mar 20, 1990
Grant Date -
N/A
app pub date -
Dec 22, 1988
filing date -
Dec 22, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The collector area of a lateral PNP transistor may be incrementally increased during an electic testing step on wafer of an integrated circuit by purposely forming an auxiliary p-type diffused collector region having fractional dimensions near the primary collector region of the transistor and by permanently shorcircuiting the two regions by means of a 'Zener zapping' technique, by forcing a current through the inversely biased base-collector junction utilizing a suitable contact pad connected to the auxiliary collector region to create localized power dissipation conditions sufficient to melt the metal of the respective metal at the adjacent contacts and to form a permanent connection between the two metals. The technique is very useful for adjusting the value of the output current(s) in precision current generating circuits.
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