Integrated circuit and method for transaction retraction
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United States of America Patent
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Mar 29, 2011
Grant Date -
Oct 2, 2008
app pub date -
Mar 15, 2005
filing date -
Mar 26, 2004
priority date (Note) -
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Abstract
An integrated circuit having a plurality of processing modules (I, T) is provided. At least one first processing module (I) issues at least one transaction towards at least one second processing module (T). Said integrated circuit further comprises at least one first transaction retraction unit (TRU1) for indicating an allowance to said at least one first of said processing modules (I) to retract said at least one transaction according to the sate of said second processing module (T).
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