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Abstract

A semiconductor memory device 100 is proposed including an internal address generation circuit 3, a first internal address control signal generation part 4, a second internal address control signal generation part 11, and an internal address control signal selection circuit 10 having an OR gate transistor 12. The internal address generation circuit 3 generates an internal address signal based on input address data. The first internal address control signal generation part 4 generates a first internal address control signal and having a function which fixes the first internal address control signal at a predetermined level with the elapse of a fixed period of time. The second internal address control signal generation part 11 generates a second internal address control signal corresponding to an input of a predetermined command. The OR gate transistor 12 transmits either the first internal address control signal or the second internal address control signal to the internal address generation circuit 3.

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First Claim