Method for fabricating a high voltage MOS transistor

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United States of America Patent

PATENT NO 5132235
SERIAL NO

07678578

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer. Using this method, the high concentration of slow diffusing N type antimony or arsenic dopant in the buried layer will not out-diffuse into the N-well region and adversely affect the breakdown voltage between the source or drain and the N-well. The out-diffusing of the phosphorus into the epitaxial layer, however, will merge with the phosphorus diffusion from the top to form a uniform N type concentration in the N-well.

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Patent Owner(s)

  • SILICONIX INCORPORATED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Blanchard, Richard A Los Altos, CA 334 6610
Busse, Robert W Mountain View, CA 4 159
Williams, Richard K Cupertino, CA 343 14821

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