Dynamic semiconductor memory reducing the frequency of occurrence of refresh command request and refresh control method thereof
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United States of America Patent
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Dec 8, 2009
Grant Date -
Oct 4, 2007
app pub date -
Jun 12, 2006
filing date -
Mar 30, 2006
priority date (Note) -
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Abstract
A dynamic semiconductor memory has a plurality of memory blocks and a memory core. Each of the memory blocks has a sense amplifier, and the memory core is formed from memory cells located at intersections between a plurality of word lines and a plurality of bit lines connected to the sense amplifier. The memory blocks are sequentially refreshed by selecting each of the word lines and by simultaneously activating the memory cells connected to the selected word line by the sense amplifier. The dynamic semiconductor memory has a first refresh counter which outputs a first internal refresh candidate address, and a second refresh counter which outputs a second internal refresh candidate address that is different from the first internal refresh candidate address. When an externally accessed address coincides with the first internal refresh candidate address, a refresh operation is performed starting from the second internal refresh candidate address.
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