Semiconductor interconnection line and method of forming the same
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United States of America Patent
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Jun 14, 2011
Grant Date -
Aug 23, 2007
app pub date -
Apr 20, 2007
filing date -
Dec 31, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.
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