Pillar-based memory hardmask smoothing and stress reduction

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United States of America Patent

PATENT NO 11812668
SERIAL NO

17552027

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Abstract

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A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

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Patent Owner(s)

  • IBM CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dutta, Ashim Clifton Park, US 91 111
Metzler, Dominik Clifton Park, US 27 392
Rizzolo, Michael Delmar, US 225 794
Standaert, Theodorus E Clifton Park, US 302 2575

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