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Abstract

A method for manufacturing an EEPROM cell including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with a stack of first and second layers, forming at least one first opening in the second layer, forming, in the first layer, a second opening continuing the first opening, enlarging the first opening by isotropic etching, forming a first doped region in the substrate by implantation through the first enlarged opening, the first doped region taking part in the forming of the transistor drain or source, forming, in the third opening, a thinned-down insulating portion thinner than the first layer, and forming the gates of the MOS transistor at least partially extending over the thinned-down insulating portion.

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First Claim