Digital circuits with adaptive resistance to single event upset
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United States of America Patent
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Sep 14, 2010
Grant Date -
Feb 19, 2009
app pub date -
Aug 17, 2007
filing date -
Aug 17, 2007
priority date (Note) -
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Abstract
A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.
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