Split charge storage node outer spacer process
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United States of America Patent
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Feb 8, 2011
Grant Date -
Apr 30, 2009
app pub date -
Oct 25, 2007
filing date -
Oct 25, 2007
priority date (Note) -
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Abstract
Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
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