Apparatus and method for implementing write assist for static random access memory arrays
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United States of America Patent
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Jul 31, 2012
Grant Date -
Sep 17, 2009
app pub date -
Mar 14, 2008
filing date -
Mar 14, 2008
priority date (Note) -
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Abstract
An apparatus for implementing a write assist for a memory array includes a common discharge node configured to provide a discharge path for precharged write data lines and bit lines selected during a write operation of the memory array; negative boost circuitry configured to introduce a voltage lower than a nominal logic low supply voltage onto the common discharge node following the discharge of the common discharge node, write data lines and bit lines; and a clamping device coupled to the common discharge node, the clamping device configured to limit the magnitude of negative voltage applied to common discharge node by the negative boost circuitry so as to prevent activation of non-selected bit switches.
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