Electrostatic discharge protection circuit
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United States of America Patent
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-
Dec 25, 2007
Grant Date -
Jul 14, 2005
app pub date -
Dec 20, 2004
filing date -
Dec 29, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Disclosed is an ESD protection circuit for use in a semiconductor memory device with enhanced ESD efficiency. The ESD protection circuit includes: an input pad for receiving a data; a data input buffer for transmitting the data inputted from the input pad to an internal circuit; a first discharging means for a HBM/MM ESD connected to the input pad; and a second discharging means provided with at least one diode for a CDM ESD, disposed between the first discharging means and the data input buffer.
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