Method and apparatus for providing pseudo 2-port RAM functionality using a 1-port memory cell
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United States of America Patent
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Apr 19, 2005
Grant Date -
May 1, 2003
app pub date -
Aug 7, 2002
filing date -
Nov 1, 2001
priority date (Note) -
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Abstract
A method and apparatus operable to provide pseudo 2-port RAM functionality using 1-port memory cells. A pseudo 2-port RAM functionality is provided using an array of 1-port memory cells to perform read and write operations during a single clock cycle. Control logic is used to determine when the read and write operations occur. The pseudo 2-port RAM uses the control logic to divide the clock cycle into four phases in accordance with a preferred embodiment. The first phase is used to set up the addresses and register values, the second phase is used to prepare for the read operation, the third phase is used to perform the read operation and prepare for the write operation, and the fourth phase performs the write operation.
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