High speed binary counter
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 5, 2006
Issued Date -
N/A
app pub date -
Nov 17, 2004
filing date -
Nov 17, 2004
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B0 and B1, and at least two AND gates for each higher order binary bit. The counter also includes an input factor delay second flip-flop. The counter is further provided with a mechanism for redundant least significant terms for lesser order bits.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully